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[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可-Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
Platform: | Size: 577536 | Author: xie | Hits:

[VHDL-FPGA-Verilog] newvhdl

Description: 在 Quartus II 7.1平台下，用VLDL写的一个计时器的程序-a timer written in VLDL in Quartus II 7.1 platform
Platform: | Size: 72704 | Author: xwl | Hits:

[VHDL-FPGA-Verilog] Timer

Description: ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
Platform: | Size: 497664 | Author: lizhuodong | Hits:

[Internet-Network] timer

Description: AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only
Platform: | Size: 1024 | Author: kkris | Hits:

[VHDL-FPGA-Verilog] Timer

Description: 计时器的设计，在Quartus II上运行通过，FOR NJU Cser。使用了signaltap-The design of the timer, run by the Quartus II, FOR NJU Cser. Used signaltap
Platform: | Size: 1926144 | Author: 戴连鹏 | Hits:

[VHDL-FPGA-Verilog] Counter

Description: 计时器的设计，在Quartus II上运行通过，简单易用，主要是For NJU CSers-The design of the timer, run by the Quartus II, easy to use, mainly For NJU CSers
Platform: | Size: 824320 | Author: 戴连鹏 | Hits:

[VHDL-FPGA-Verilog] RS232_FIR

Description: Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer / Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis-Quartus II was a development tool of CPLD/FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer/Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis
Platform: | Size: 202752 | Author: jay | Hits:

[VHDL-FPGA-Verilog] clock-with-alarm-and-timer

Description: 黑金EP2C5QC808N系列，Quartus 11.0 中编译综合的数字钟，具有实时时钟运行，时钟校准，整点报时以及定时提醒功能，包含全部的工程文件。-Black EP2C5QC808N series, Quartus 11 compilation and synthesis of digital clock, with real-time clock operation, calibration of the clock, the whole point timekeeping, timing remind function, including all engineering documents.
Platform: | Size: 2658304 | Author: 姜伟 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字计时器的vhdl实现，quartus 和 modelsim 仿真-Digital timer vhdl achieve quartus and modelsim simulation
Platform: | Size: 4528128 | Author: 金浩强 | Hits:

[VHDL-FPGA-Verilog] Timer

Description: Verilog编写的多功能秒表，Quartus仿真及硬件测试通过。-Verilog prepared by the multi-function stopwatch, Quartus simulation and hardware testing through.
Platform: | Size: 1686528 | Author: styx | Hits:

[Windows Develop] digital_clock

Description: QUARTUS中实现数字钟，有计时计分计秒的功能，整点报时的功能，用VERILOG实现。-QUARTUS achieve digital clock, a timer function scoring the seconds, the whole point timekeeping function, using VERILOG implementation.
Platform: | Size: 698368 | Author: 吉莉 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 定时器功能，主函数。nios2 quartus-nios2 quartus main
Platform: | Size: 1024 | Author: ma | Hits:

[Internet-Network] timer

Description: AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only
Platform: | Size: 1024 | Author: eseco | Hits:

[Other Embeded program] DE0_mpu6050_uart_timer

Description: 基于DE0开发板的MPU6050数据采集，同时使用定时器，同时每一毫秒从串口发送数据，包含Quartus硬件电路部分-DE0 based development board MPU6050 data collection, using a timer, but every millisecond to send data from the serial port, including hardware circuit part Quartus
Platform: | Size: 8192 | Author: wangke | Hits:

[VHDL-FPGA-Verilog] led

Description: FPGA做的led流水灯，quartus搭的nios，计时器每隔一秒led点亮一次，四个流水灯循环显示，适合新手学习-FPGA do led light water, quartus ride nios, timer once every second led lights, four light water cycle, for beginners to learn
Platform: | Size: 14083072 | Author: 勇磊 | Hits:

[Software Engineering] the-digital-clock

Description: 本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片，利用 VHDL 语言采用自 顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计，最后在实验箱上进行测 试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐 闹铃。-The design uses the silicon chip EP1C12Q240C8 produced by the company of ALTERA. And with the help of VHDL, the design of a digital clock is completed using the top-down approach under Quartus Ⅱ, finally carried out in the SmartSOPC. Functions of the digital clock are: timer, showing day, setting time, resetting, Chime on every hour, and alarm with music.
Platform: | Size: 231424 | Author: 费孝海 | Hits:

[Other] exp15_demo.ZIP

Description: 实验例程15，在QUARTUS环境下使用计时器点亮LED灯-Experiment 15 routines, use the timer lit LED lights in the QUARTUS environment
Platform: | Size: 1024 | Author: 杨米 | Hits:

[VHDL-FPGA-Verilog] test6_timer

Description: 这是有Quartus II和Nios II共同协作完成的基于FPGA的异步电机矢量控制系统，里面包含定时器，LCD显示，温度检测等内容-This is the Quartus II and Nios II work together to complete induction motor vector control system based on FPGA, contains a timer, LCD display, temperature detection, etc
Platform: | Size: 19980288 | Author: hurongxueyue | Hits:

[VHDL-FPGA-Verilog] quartus-II

Description: 用Quartus II实现答辩计时器设置，大致功能有时间显示，倒计时提醒，暂停键等。-Quartus II realized by the respondent timer settings, roughly the time display function, countdown reminder, the pause button and so on.
Platform: | Size: 485376 | Author: 边松林 | Hits:
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